| Published Papers |
| No. | Title, Author, Journal, Vol( No), Start Page- End Page, Date of publication, DOI, URL
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| 1 | Experimental Implementation of Fault Tolerance Using Dynamic Partial Reconfiguration on Xilinx Zynq-7000 SoC, Seiya Ogido, Shuichi Ichikawa, Naoki Fujieda, Chikatoshi Yamada, Kei Miyagi, IEEJ Transactions on Industry Applications, 141( 2), 93- 99, Feb. 2021, 10.1541/ieejias.141.93,  |
| 2 | Random Number Generation from Internal LFSR and Fluctuation of Sampling Interval, Hidetaka Masaoka, Shuichi Ichikawa, Naoki Fujieda, IEEJ Transactions on Industry Applications, 141( 2), 86- 92, Feb. 2021, 10.1541/ieejias.141.86, |
| 3 | On the Feasibility of TERO-Based True Random Number Generator on Xilinx FPGAs, Naoki Fujieda, 30th International Conference on Field-Programmable Logic and Applications (FPL), , 103- 108, Aug. 2020, 10.1109/fpl50879.2020.00027, |
| 4 | An Analysis of DCM-Based True Random Number Generator, Naoki Fujieda, Masaaki Takeda, Shuichi Ichikawa, IEEE Transactions on Circuits and Systems II: Express Briefs, 67( 6), 1109- 1113, Jun. 2020, 10.1109/tcsii.2019.2926555, |
| 5 | A light-weight implementation of latch-based true random number generator, Naoki Fujieda, Yusuke Ayuzawa, Masato Hongo, Shuichi Ichikawa, 15th International Wireless Communication and Mobile Computing Conference (IWCMC 2019), , 901- 906, Jun. 2019, 10.1109/IWCMC.2019.8766516, |
| 6 | An Analysis on Randomness of Path ORAM for Light-weight Implementation, Hiroki Fujita, Naoki Fujieda, Shuichi Ichikawa, 6th Workshop on Computer Systems and Architectures (CSA-6) held in conjunction with CANDAR '18, , , Nov. 2018, 10.1109/CANDARW.2018.00037, |
| 7 | A Multiple Clock Domain Design of High-radix Montgomery Multiplication for Simplicity, Naoki Fujieda, Yusuke Ayuzawa, Masato Hongo, Shuichi Ichikawa, 2018 IEEE Region 10 International Conference (TENCON2018), , , Oct. 2018, 10.1109/TENCON.2018.8650219, |
| 8 | Attenuation Model for Error Correction of Ultrasonic Positioning System, Naoki Fujieda, Takumi Shinohara, Shuichi Ichikawa, Yuhki Sakaguchi, Shunsuke Matsuoka, Hideki Kawaguchi, IEEJ Journal of Industry Applications, 7( 2), 181- 188, Mar. 2018, 10.1541/ieejjia.7.181, |
| 9 | An Obfuscated Hardwired Sequence Control System Generated by High Level Synthesis, Yoshiki Ishigaki, Naoki Fujieda, Yuumi Matsuoka, Kazuki Uyama, Shuichi Ichikawa, 5th Workshop on Computer Systems and Architectures (CSA-5) held in conjunction with CANDAR '17, , , Nov. 2017, 10.1109/CANDAR.2017.29, |
| 10 | A Virtual Cache for Overlapped Memory Accesses of Path ORAM, Naoki Fujieda, Ryo Yamauchi, Hiroki Fujita, Shuichi Ichikawa, International Journal of Networking and Computing, 7( 2), 106- 123, Jul. 2017, , |
| 11 | Evaluation of the hardwired sequence control system generated by high-level synthesis, Naoki Fujieda, Shuichi Ichikawa, Yoshiki Ishigaki, Tasuku Tanaka, 2017 IEEE International Symposium on Industrial Electronics (ISIE 2017), , 1261- 1267, Jun. 2017, 10.1109/ISIE.2017.8001426, |
| 12 | Last Path Caching: A Simple Way to Remove Redundant Memory Accesses of Path ORAM, Naoki Fujieda, Ryo Yamauchi, Shuichi Ichikawa, 4th Workshop on Computer Systems and Architectures (CSA-4) held in conjunction with CANDAR '16, , 347- 353, Nov. 2016, 10.1109/CANDAR.2016.0068, |
| 13 | Design and Implementation of Instruction Indirection for Embedded Software Obfuscation, Naoki Fujieda, Tasuku Tanaka, Shuichi Ichikawa, Microprocessors and Microsystems, 45( A), 115- 128, Aug. 2016, 10.1016/j.micpro.2016.04.005, |
| 14 | A complement to Enhanced Instruction Register File against Embedded Software Falsification, Naoki Fujieda, Kiyohiro Sato, Shuichi Ichikawa, 5th Program Protection and Reverse Engineering Workshop (PPREW-5), ( 3), , Dec. 2015, 10.1145/2843859.2843864, |
| 15 | An XOR-based Parameterization for Instruction Register Files, Naoki Fujieda, Shuichi Ichikawa, IEEJ Transactions on Electrical and Electronic Engineering, 10( 5), 592- 602, Sep. 2015, 10.1002/tee.22123, |
| 16 | S-Box Absorption Design for Key-Specific AES circuits, Shunsuke Matsuoka, Naoki Fujieda, Shuichi Ichikawa, International Conference of Global Network for Innovative Technology (IGNITE2014), , 316- 319, Dec. 2014, ,
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| 17 | Design Trade-offs in SHA-3 Multi-Message Hashing on FPGAs, Yusuke Ayuzawa, Naoki Fujieda, Shuichi Ichikawa, 2014 IEEE Region 10 International Conference (TENCON2014), ( 99), , Oct. 2014, 10.1109/TENCON.2014.7022311, |
| 18 | Enhanced Instruction Register Files for Embedded Software Obfuscation, Naoki Fujieda, Shuichi Ichikawa, 29th International Conference on Computers and Their Applications (CATA-2014), , 153- 158, Mar. 2014, ,
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| 19 | An XOR-based approach to merging entries for instruction register files, Naoki Fujieda, Shuichi Ichikawa, First Workshop on Computer Systems and Architectures (CSA-1) held in conjunction with CANDAR'13, , 332- 337, Dec. 2013, 10.1109/CANDAR.2013.60, |
| 20 | Request Density Aware Fair Memory Scheduling, Takakazu Ikeda, Shinya Takamaeda-Yamazaki, Naoki Fujieda, Shimpei Sato, Kenji Kise, 3rd JILP Workshop on Computer Architecture Competitions (JWAC-3) in conjunction with ISCA-2012, , , Jun. 2012, , |
| 21 | ScalableCore System: A Scalable Many-core Simulator by Employing Over 100 FPGA, Shinya Takamaeda, Shintaro Sano, Yoshito Sakaguchi, Naoki Fujieda, Kenji Kise, 8th International Symposium on Applied Reconfigurable Computing (ARC2011), , 138- 150, Mar. 2012, 10.1007/978-3-642-28365-9_12, |
| 22 | A Partitioning Method of Cooperative Caching with Hit Frequency Counters for Many-Core Processors, Naoki Fujieda, Kenji Kise, Third Workshop on Ultra Performance and Dependable Acceleration Systems (UPDAS-3) held in conjunction with ICNC'11, , 160- 165, Dec. 2011, 10.1109/ICNC.2011.31, |
| 23 | Rethinking Processor Instruction Fetch: Inefficiencies-Cracking Mechanism, Mochamad Asri, Naoki Fujieda, Kenji Kise, 2011 International SoC Design Conference (ISOCC2011), , 207- 210, Nov. 2011, 10.1109/ISOCC.2011.6138746, |
| 24 | SimMips: A MIPS System Simulator, Naoki Fujieda, Takefumi Miyoshi, Kenji Kise, Workshop on Computer Architecture Education(WCAE) held in conjunction with MICRO-42, , 32- 39, Dec. 2009, , |
| 25 | ScalableCore : High-Speed Prototyping System for Many-Core Processors, Shinya Takamaeda, Shimpei Watanabe, Shimpei Sato, Koh Uehara, Yuhta Wakasugi, Naoki Fujieda, Yosuke Mori, Kenji Kise, International Symposium on Low-Power and High-Speed Chips (COOL Chips), , 161- , Apr. 2009, ,
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| 26 | SimCell: A Processor Simulator for Multi-Core Architecture Research, Shimpei Sato, Naoki Fujieda, Akira Moriya, Kenji Kise, IPSJ Transactions on Advanced Computing Systems, 2( 1), 146- 157, Mar. 2009, 10.2197/ipsjtrans.2.81, |
| 27 | MipsCoreDuo: A Multifunction Dual-core Processor, Yuhta Wakasugi, Naoki Fujieda, Shinya Takamaeda, Kenji Kise, International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS2009), , 587- 590, Jan. 2009, 10.1109/ISPACS.2009.5383772, |
| 28 | Processor Simulator SimCell to Accelerate Research on Many-core Processor Architectures, Shimpei Sato, Naoki Fujieda, Akira Moriya, Kenji Kise, Workshop on Cell Systems and Applications (WCSA 2008) held in conjunction with ISCA-2008, , 119- 127, Jun. 2008, ,
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